The VLSI Systems Research Group of the Surrey Space Centre (SSC) has a long-term research programme, codenamed ChipSat, which aims to apply advanced micro- and nano- technologies to small satellite design [1 ]. A specification of a system-on-a-chip (SoC) for small satellite data processing and control was developed. The goal is to implement an on-board data handling (OBDH) system of a small satellite on a single mixed-mode application specific integrated circuit (ASIC) chip. The specification of the SoC is based on requirements derived for future satellite missions of Surrey Satellite Technology Ltd. (SSTL) and therefore includes provisions for enhanced remote sensing and data gathering capabilities.
The implementation of an entire OBDH system in the form of a single mixed-mode ASIC chip can be expensive. A financially viable implementation option is to use high-density field-programmable gate arrays (FPGAs). FPGAs offer a number of advantages that are very relevant to the specifics of small satellite design: flexibility of design, shorter time-to-market, lower cost, remote reconfigurability, etc. High-density FPGAs are becoming the preferred implementation platform in a number of terrestrial applications previously dominated by application specific integrated circuits (ASICs). So far high-density FPGAs have mostly been used in payload systems of small satellites, however introduction of radiation hardened versions of such devices by leading manufacturers as XILINX and Actel paves the way for their use in main on-board electronic systems.
A single chip implementation of a simplified version of an on-board computer (OBC) is in a process of prototyping on a high-density programmable logic chip using soft intellectual property (IP) cores. The system-on-a-chip OBC (SoC-OBC) is modelled on a simplified version of an on-board computer designed by SSTL. The SoC-OBC is based on the LEON microprocessor IP core - a full featured 32-bit SPARC V8 compatible RISC core, developed by ESA. A number of peripheral IP cores were developed such as a floating-point mathematical co-processor, a DMA controller, an Ethernet controller, and an FSK modem. A downsized implementation of the SoC-OBC consisting of a microprocessor core, a CAN core and an EDAC core was successfully integrated on a XILINX Virtex FPGA. Work has started on the development of an image compression engine. The real-time operating system RTEMS was successfully configured with the LEON processor and tested with application and benchmark programs.
A floating-point CORDIC-based co-processor IP core has been developed and integrated with the LEON microprocessor core on a XILINX Virtex FPGA. The coprocessor is capable of evaluating 17 functions such as addition, multiplication, division square root trigonometric, hyperbolic functions, exp, and natural log. The coprocessor operation and performance were evaluated with a number of test programs, including the whetstone benchmark program, the execution of which was speeded up by 60%.
The downsized SoC-OBC (LEON+CAN+EDAC) requires about 50% of the capacity of a XILINX Virtex XCV800 FPGA. The bitstream file of the implemented subsystem measures 576 Kbytes. Estimates of the area of the entire SoC-OBC (without the co-processor) indicate that it fits in about three quarters of the chip. The co-processor, which is still in a process of testing, takes approximately half of an XCV800 chip. Hence the complete OBC system will not fit in a Virtex XCV800 chip, however, a larger Virtex chip, for example, Virtex XCV2000E, will be able to house the implementation of the whole system.
A simplified communication system, specifically designed to meet the needs of a single chip on-board computer has been developed. The system represents a streamlined, yet reliable and automated, standalone software implementation of the Consultative Committee of Space Data Systems (CCSDS) protocol. The CCSDS protocol is a standard space industry communication protocol employed on numerous missions ranging from relatively simple low-earth orbit missions to deep space probes. The software package features a modular structure, which can facilitate easy expansions of functionality to suit specific mission requirements. The software imposes minimal memory footprint and performance requirements on the OBC. The functionality of the package has been verified via simulation.
The size of the CCSDS software is as follows: Ground segment (including the R-S decoder) - 177 Kbytes; Spacecraft segment (including the R-S encoder) - 176 Kbytes; R-S code: 21.7Kbytes. The R-S encoder/decoder program used in the TLM coding system is derived from a public domain program (rs.c written by Phil Karn). The R-S code is compliant with the coding algorithm in the CCSDS recommendations.
Satellite electronic components are generally unavailable for physical upgrade or repair after launch in space. An on-going research project explores run-time reconfigurable SRAM-based FPGAs for the purpose of remote restructuring of onboard digital systems. A scheme for remote run-time reconfiguration of on-board programmable logic components over Internet has been proposed.
Specification and feasibility assessment of the SoC-OBC were reported in [ 2, 3]. Reconfiguration issues of the SoC-OBC were reported in [4 ]. Recent research results concerned with the implementation of a main subsystem of the SoC-OBC and the development of a software communication system were presented in [5 , 6]. The work on the floating-point CORDIC co-processor is detailed in [ 7, 8, 9].
Work is underway on efficient lossless compression of satellite images on-board a small satellite. The adopted approach to lossless image compression employs predictive neural networks (NN), integer wavelet transforms (IWT) and Peano-Hilbert scan. Test results derived from a set of grey-scale satellite images taken by UoSat-12 have shown that the proposed NN-based technique yields higher compression ratios than state-of-the-art lossless compression methods, such as the Rice algorithm and JPEG2000 [ 10, 11, 12]. A hardware implementation that can improve significantly the overall speed of the compressor is proposed which is based on multiple redundant neural processors operating in parallel [13 ]. Implementation of the JPEG2000 lossless compression standard as a peripheral module for integration with the LEON processor in the SoC-OBC has been initiated.
Digital satellite images are vulnerable to theft and can become a subject of piracy during both transmission and arrival at the ground station. Digital watermarking is proposed as a solution to copyright protection. An ongoing research project is concerned with the development of a novel high-speed on-board watermarking method suitable for VLSI implementation . The proposed watermarking method satisfies the invisibility and robustness requirements and supports reversibility of the watermarking scheme.
1. T. Vladimirova. Next Generation Satellites: Picosatellites & Satellites-on-a-Chip - OSCAR News, Amsat UK, October 2000, N 145, pp 28-37.
2. H.Tiggeler, T.Vladimirova, D.Zheng. A System-on-a-Chip for Small Satellite Data Processing and Control, Proceedings of 4th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'2000), P20, September 2000, Laurel, Maryland US, NASA.
3. H.Tiggeler, T.Vladimirova, J.Gaisler. Designing a System-on-a-chip for Small Satellite Data Processing and Control, IIE Magazine on Engineering Technology, vol. 4, N 6, June 2001, pp. 38-42 .
4. D.Zheng, T.Vladimirova, H.Tiggeler, M.Sweeting. Reconfigurable Single-Chip On-Board Computer for a Small Satellite, 52nd International Astronautical Congress, Toulouse, France, October 1-5, 2001, IAF-01-U3.09.
5. I.Rutter, T.Vladimirova, H.Tiggeler. A CCSDS Software System for a Single-Chip On-Board Computer of a Small Satellite - 15th AIAA/Utah Sate University Conference on Small Satellites, Utah, USA, August 13-16 2001, SSC01-VI-4.
6. D.Zheng, T.Vladimirova, M.N.Sweeting. A CCSDS-Based Communication System for a Single Chip On-Board Computer", Proceedings of the 5th Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'2002), D5, September 2002, Laurel, Maryland, US, NASA.
7. T.Vladimirova, H.Tiggeler. FPGA Implementation of Sine and Cosine Generators Using the CORDIC Algorithm, in Proceedings of the 3rd Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD'99), A-2, 28-30 September 1999, Laurel, Maryland, US, NASA.
8. T.Vladimirova, D.Eamey. 32-Bit Floating-Point Mathematical CORDIC Co-Processor - submitted to the 13th International Conference on Field Programmable Logic and Applications, September 1-3, 2003, Lisbon, Portugal.
9. T.Vladimirova, D.Eamey, S.Keller, M.Sweeting. Floating-Point Mathematical Co-Processor for a Single Chip On-Board Computer - submitted to the 6th Military and Aerospace Applications of Programmable Logic Devices and Technologies International Conference (MAPLD'2003), September 9-11, 2003, Washington DC, US, NASA.
10. S.Atek, T.Vladimirova. "A New Lossless Compression Method for Small Satellite On-Board Imaging" Proceeding of the 3rd WSEAS International Conference on Applied and Theoretical Mathematics, Miedzyzdroje, Poland, September 1-5, 2002, ed. N.E.Mastorakis, pp. 1871-1876, 2002
11. S.Atek, T.Vladimirova, P.Sweeney. "Lossless Compression for Small Satellite On- Board Imaging" in Recent Trends in Multimedia Information Processing, Proceeding of the 9th International Workshop on Systems, Signals and Image Processing IWSSIP'02, Manchester, November 7-8, 2002, pp. 249-255, World Scientific Publishing Co.Pte.Ltd., 2002.
12. S.Atek, T.Vladimirova, P.Sweeney. "Neural Network Based On-Board Lossless Image Compression" in Recent Trends in Multimedia Information Processing, Proceeding of the 9th International Workshop on Systems, Signals and Image Processing IWSSIP'02, Manchester, November 7-8, 2002, pp. 489-495, World Scientific Publishing Co.Pte.Ltd., 2002.
13. S.Atek and T.Vladimirova. Fast Neural Network Based On-Board Image Compressor - accepted for the 54th International Astronautical Congress, IAC-03-B.6.08, Sept. 29 - Oct. 3, 2003, Bremen, Germany.
14. A.Chikouche, P.Seeney, T.Vladimirova. Robust Watermarking
Method Using a Fast Algorithm. 4th European Workshop on Image Analysis and Multimedia
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