The activities of the VLSI Systems Research Group are related
to efficient system design involving front-end micro- and nano- technologies,
advanced software development and biologically inspired artificial intelligence
techniques. The projects carried out by the group cover the following areas:
Algorithms and Structures for High-Speed On-Board Data and Image Processing
The ChipSat research programme aims in the long-term to investigate technological, design, communication and algorithmic aspects of femto-satellites (weighing less than 100 grams) and virtual-satellite missions based on femto-satellite nodes. Currently the research is focused on miniaturisation of the on-board data handling system of a small satellite.
Work has continued on the design of a system-on-a-chip (SoC) for small satellite data processing and control. A single-chip implementation of a simplified version of an on-board computer (OBC) is in a process of prototyping on a high-density programmable logic chip using soft intellectual property (IP) cores. The OBC is based on the LEON microprocessor IP core - a full featured 32-bit SPARC V8 compatible RISC core, developed by ESA. A number of peripheral IP cores were developed such as a floating-point mathematical co-processor, a DMA controller, an Ethernet controller, and an FSK modem. A downsized implementation of the SoC OBC consisting of a microprocessor core, a CAN core and an EDAC core was successfully integrated on a XILINX Virtex FPGA. Work has started on the development of an image compression engine. The real-time operating system RTEMS was successfully configured with the LEON processor and tested with application and benchmark programs.
A simplified communication system, specifically designed to meet the needs of a single-chip on-board computer has been developed. The system represents a streamlined, yet reliable and automated, standalone software implementation of the CCSDS protocol. The software package features a modular structure, which can facilitate easy expansions of functionality to suit specific mission requirements. The software imposes minimal memory footprint and performance requirements on the OBC. The functionality of the package has been verified via simulation.
Satellite electronic components are generally unavailable for physical upgrade or repair after launch in space. This research explores run-time reconfigurable SRAM-based FPGAs for the purpose of remote restructuring of on-board digital systems. Investigation into the suitability of the XILINX Virtex FPGAs and the JBits design environment for run-time reconfiguration was carried out. A scheme for remote run-time reconfiguration of on-board programmable logic components over Internet has been proposed.
Computer Arithmetic. The main objective of this research is to speed up the execution of computationally intensive on-board data processing routines via effective hardware implementation. A floating-point CORDIC-based co-processor IP core has been developed and integrated with the LEON microprocessor core on a XILINX Virtex FPGA. The co-processor is capable of evaluating 17 functions such as addition, multiplication, division square root trigonometric, hyperbolic functions, and log. The co-processor operation and performance were evaluated with a number of test programs, including the Whetstone benchmark program, the execution of which was speeded up by 60%.
Image Compression. Work is underway on efficient lossless
compression of satellite images on-board a small satellite. The adopted approach
to lossless image compression employs predictive neural networks (NN), integer
wavelet transforms (IWT) and Peano-Hilbert scan. Test results derived from a
set of gray-scale satellite images taken by UoSat12 (a mini-satellite developed
by SSTL) have shown that the proposed NN-based technique yields higher compression
ratios than state-of-the-art lossless compression methods, such as the Rice
algorithm and JPEG2000. A hardware implementation that can improve significantly
the overall speed of the compressor is proposed which is based on multiple redundant
neural processors operating in parallel.
Image Watermarking. Digital satellite images are vulnerable to theft and can become a subject of piracy during both transmission and arrival at the ground station. Digital watermarking is proposed as a solution to copyright protection. This research is concerned with the development of a novel high-speed on-board watermarking method suitable for VLSI implementation. The proposed watermarking method satisfies the invisibility and robustness requirements and supports reversibility of the watermarking scheme.
Application of Self-Organising Neural Networks to SAR Target
Recognition. This project aims to demonstrate the
effectiveness of a set of computational neural components in an on-board Synthetic
Aperture Radar (SAR) target learning and recognition system. Work has continued
on application of Adaptive Resonance Theory (ART) neural networks to SAR target
recognition with an emphasis upon improving tolerance to noise. Modified algorithms
that improve the performance of the Fuzzy ART NN when presented with noisy input
patterns have been developed. The algorithms have been applied to the MSTAR
SAR imagery. Extensive experimentation has been carried out by means of an improved
and expanded ART simulator.