"SEE Analysis and Mitigation for FPGA and Digital ASIC Devices"


The talk gives an overview about R&D activities at the ESA Microelectronics Section relating to Single Event Effects (SEE). Tools for analysis, simulation and emulation of Single Event Upsets (SEU) in ASIC and FPGA design are introduced. SEU effects in SRAM based reprogrammable FPGA and mitigation methods are discussed. Protection methods against SEU in embedded user memories and various schemes to mitigate SEU and Single Event Transients (SET) in ASIC are presented, in particular the voted triple modular redundancy (TMR) cell with three time-spread clock domains. Impacts on complexity, performance, power consumption and the ASIC design flow (clock tree, hold fix etc.), are discussed.